Invention Grant
- Patent Title: Scalable runtime validation for on-device design rule checks
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Application No.: US17132306Application Date: 2020-12-23
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Publication No.: US11556677B2Publication Date: 2023-01-17
- Inventor: Furkan Turan , Patrick Koeberl , Alpa Trivedi , Steffen Schulz , Scott Weber
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G06F21/85 ; G06N3/04 ; H04L9/08 ; G06F9/30 ; G06F9/50 ; G06F15/177 ; G06F15/78 ; H04L9/40 ; G06F11/07 ; G06F30/331 ; G06F9/38 ; G06F11/30 ; G06F119/12 ; G06F21/76 ; G06N3/08 ; H04L9/00 ; G06F111/04 ; G06F30/31 ; G06F21/30 ; G06F21/53 ; G06F21/57 ; G06F21/73 ; G06F21/74 ; G06N20/00 ; G06F21/71 ; G06F21/44

Abstract:
An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.
Public/Granted literature
- US20210110099A1 SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS Public/Granted day:2021-04-15
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