Invention Grant
- Patent Title: Integrated circuit layout method and system
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Application No.: US17209918Application Date: 2021-03-23
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Publication No.: US11556688B2Publication Date: 2023-01-17
- Inventor: Jian-Sing Li , Hui-Zhong Zhuang , Jung-Chan Yang , Ting Yu Chen , Ting-Wei Chiang , Tzu-Ying Lin , Li-Chun Tien
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F30/392
- IPC: G06F30/392 ; H01L27/02

Abstract:
A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.
Public/Granted literature
- US20210209284A1 INTEGRATED CIRCUIT LAYOUT METHOD AND SYSTEM Public/Granted day:2021-07-08
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