公开(公告)号：US11943939B2

公开(公告)日：2024-03-26

申请号：US17140441

申请日：2021-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Kai Hsu ,  Jerry Chang Jui Kao ,  Chin-Shen Lin ,  Ming-Tao Yu ,  Tzu-Ying Lin ,  Chung-Hsing Wang

IPC: H10K19/10 ,  H01L21/822 ,  H01L27/06 ,  H01L49/02 ,  H10K19/00

CPC classification number: H10K19/10 ,  H01L21/822 ,  H01L27/0688 ,  H01L28/10 ,  H01L28/40 ,  H10K19/201

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

公开(公告)号：US12218670B2

公开(公告)日：2025-02-04

申请号：US18333402

申请日：2023-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： I-Wen Wang ,  Po-Chih Cheng ,  Jia-Hong Gao ,  Kuang-Ching Chang ,  Tzu-Ying Lin ,  Jerry Chang Jui Kao

IPC: H03K3/3562

Abstract: An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors in at least one strong active-region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors in at least one weak active-region structure. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.

公开(公告)号：US20240361383A1

公开(公告)日：2024-10-31

申请号：US18770809

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318541 ,  G01R31/318555

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

公开(公告)号：US20210099161A1

公开(公告)日：2021-04-01

申请号：US17026423

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Shao-Lun Chien

IPC: H03K3/037 ,  G01R31/3177 ,  G01R31/317

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

公开(公告)号：US12040800B2

公开(公告)日：2024-07-16

申请号：US18064961

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Shao-Lun Chien

IPC: H03K3/03 ,  G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K3/0372 ,  G01R31/31725 ,  G01R31/3177 ,  H03K19/20

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

公开(公告)号：US12009824B2

公开(公告)日：2024-06-11

申请号：US18065327

申请日：2022-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Hui-Zhong Zhuang ,  Chi-Lin Liu

IPC: H03K3/037 ,  G06F1/12 ,  H03K19/20

CPC classification number: H03K3/037 ,  G06F1/12 ,  H03K19/20

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

公开(公告)号：US11632102B2

公开(公告)日：2023-04-18

申请号：US17338199

申请日：2021-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yung-Chen Chien ,  Xiangdong Chen ,  Hui-Zhong Zhuang ,  Tzu-Ying Lin ,  Jerry Chang Jui Kao ,  Lee-Chung Lu

IPC: H03K3/3562 ,  H03K3/037 ,  H03K3/012

Abstract: A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

公开(公告)号：US11558040B2

公开(公告)日：2023-01-17

申请号：US17026423

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Shao-Lun Chien

IPC: H03K3/03 ,  H03K3/037 ,  G01R31/317 ,  G01R31/3177 ,  H03K19/20

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

公开(公告)号：US11556688B2

公开(公告)日：2023-01-17

申请号：US17209918

申请日：2021-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jian-Sing Li ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ting Yu Chen ,  Ting-Wei Chiang ,  Tzu-Ying Lin ,  Li-Chun Tien

IPC: G06F30/392 ,  H01L27/02

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.

公开(公告)号：US20240333265A1

公开(公告)日：2024-10-03

申请号：US18738225

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Shao-Lun Chien

IPC: H03K3/037 ,  G01R31/317 ,  G01R31/3177 ,  H03K19/20

CPC classification number: H03K3/0372 ,  G01R31/31725 ,  G01R31/3177 ,  H03K19/20

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.