Memory devices might include an array of memory cells including a plurality of strings of series-connected memory cells, a plurality of access lines, a common source, a plurality of data lines, a plurality of shield lines, and control logic. Each access line might be connected to a control gate of a respective memory cell of each string of series-connected memory cells. Each string of series-connected memory cells might be selectively connected between the common source and a respective data line. The plurality of shield lines might be interleaved with the plurality of data lines. The control logic might be configured to implement a program verify operation of respective memory cells coupled to a selected access line including sensing a voltage level on each data line to determine whether each respective memory cell coupled to the selected access line has been programmed to a target level for the respective memory cell.