Invention Grant
- Patent Title: TSV coupled integrated circuits and methods
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Application No.: US17077532Application Date: 2020-10-22
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Publication No.: US11569219B2Publication Date: 2023-01-31
- Inventor: Rahul Mathur , Xiaoqing Xu , Andy Wangkun Chen , Mudit Bhargava , Brian Tracy Cline , Saurabh Pijuskumar Sinha
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Pramudji Law Group PLLC
- Agent Ari Pramudji
- Main IPC: H01L27/02
- IPC: H01L27/02 ; G06F30/31 ; H01L21/768 ; H01L23/535 ; H01L25/065 ; H01L25/00

Abstract:
According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.
Public/Granted literature
- US20220130816A1 TSV Coupled Integrated Circuits and Methods Public/Granted day:2022-04-28
Information query
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