Invention Grant
- Patent Title: Leveraging low power states for fault testing of processing cores at runtime
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Application No.: US17556473Application Date: 2021-12-20
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Publication No.: US11573872B2Publication Date: 2023-02-07
- Inventor: Jonah Alben , Sachin Idgunji , Jue Wu , Shantanu Sarangi
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Taylor English Duma L.L.P.
- Main IPC: G06F11/267
- IPC: G06F11/267 ; G06F11/22 ; G06F11/273 ; G06F11/27 ; G06F1/3296

Abstract:
In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.
Public/Granted literature
- US20220114069A1 LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME Public/Granted day:2022-04-14
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