Invention Grant
- Patent Title: Instruction caching scheme for memory devices
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Application No.: US16883769Application Date: 2020-05-26
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Publication No.: US11586547B2Publication Date: 2023-02-21
- Inventor: Crescenzo Attanasio , Massimo Iaculo , Pasquale Cimmino , Nicola Cavaliere , Francesco Falanga
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0875 ; G06F9/30

Abstract:
Methods, systems, and devices for an enhanced instruction caching scheme are described. A memory controller may include a first closely-coupled memory component that is associated with storing data and control information and a second closely-coupled memory component that is associated with storing control information. The memory controller may be configured to retrieve data from the first memory closely-coupled component and control information from a second closely-coupled memory component. Control information may be stored in the first closely-coupled memory component, and a memory controller may access the control information stored in the first closely-coupled memory component by transferring, from the first closely-coupled memory component, the control information into the second closely-coupled memory component. After transferring the control information into the second closely-coupled memory component, the memory controller may access the control information from the second closely-coupled memory component.
Public/Granted literature
- US20210374061A1 INSTRUCTION CACHING SCHEME FOR MEMORY DEVICES Public/Granted day:2021-12-02
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