An array layout of VCSELs is intentionally mis-aligned with respect to the xy-plane of the device structure as defined by the crystallographic axes of the semiconductor material. The mis-alignment may take the form of skewing the emitter array with respect to the xy-plane, or rotating the emitter array. In either case, the layout pattern retains the desired, row/column structure (necessary for dicing the structure into one-dimensional arrays) while reducing the probability that an extended defect along a crystallographic plane will impact a large number of individual emitters.