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公开(公告)号：US20190173265A1
公开(公告)日：2019-06-06
申请号：US16194980
申请日：2018-11-19
申请人： II-VI Delaware, Inc.
摘要： An array layout of VCSELs is intentionally mis-aligned with respect to the xy-plane of the device structure as defined by the crystallographic axes of the semiconductor material. The mis-alignment may take the form of skewing the emitter array with respect to the xy-plane, or rotating the emitter array. In either case, the layout pattern retains the desired, row/column structure (necessary for dicing the structure into one-dimensional arrays) while reducing the probability that an extended defect along a crystallographic plane will impact a large number of individual emitters.
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公开(公告)号：US11594860B2
公开(公告)日：2023-02-28
申请号：US16194980
申请日：2018-11-19
申请人： II-VI Delaware, Inc.
摘要： An array layout of VCSELs is intentionally mis-aligned with respect to the xy-plane of the device structure as defined by the crystallographic axes of the semiconductor material. The mis-alignment may take the form of skewing the emitter array with respect to the xy-plane, or rotating the emitter array. In either case, the layout pattern retains the desired, row/column structure (necessary for dicing the structure into one-dimensional arrays) while reducing the probability that an extended defect along a crystallographic plane will impact a large number of individual emitters.
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