Invention Grant
- Patent Title: Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells
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Application No.: US17733724Application Date: 2022-04-29
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Publication No.: US11595058B1Publication Date: 2023-02-28
- Inventor: Naveen Kumar , Shuhei Tanakamaru , Erich Franz Haratsch
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Fremont
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Fremont
- Agency: Mueting Raasch Group
- Main IPC: H03M13/01
- IPC: H03M13/01 ; H03M13/11 ; H03M13/39

Abstract:
Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.
Information query
IPC分类: