公开(公告)号：US20210328597A1

公开(公告)日：2021-10-21

申请号：US16849491

申请日：2020-04-15

Applicant: Seagate Technology LLC

Inventor： Naveen Kumar ,  Shuhei Tanakamaru ,  Erich Franz Haratsch

IPC: H03M13/01 ,  H03M13/11 ,  H03M13/39

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

公开(公告)号：US11595058B1

公开(公告)日：2023-02-28

申请号：US17733724

申请日：2022-04-29

Applicant: Seagate Technology LLC

Inventor： Naveen Kumar ,  Shuhei Tanakamaru ,  Erich Franz Haratsch

IPC: H03M13/01 ,  H03M13/11 ,  H03M13/39

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

公开(公告)号：US11307806B2

公开(公告)日：2022-04-19

申请号：US16936348

申请日：2020-07-22

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Shuhei Tanakamaru ,  Ryan James Goss ,  Dana Lynn Simonson ,  Erich Franz Haratsch

IPC: G06F3/06

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a queue depth for the request queue, determining a target interval based on the queue depth and a target queue depth, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

公开(公告)号：US11614865B2

公开(公告)日：2023-03-28

申请号：US17724053

申请日：2022-04-19

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Shuhei Tanakamaru ,  Dana Lynn Simonson ,  Erich Franz Haratsch

IPC: G06F3/06 ,  G06F9/48

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

公开(公告)号：US11349495B2

公开(公告)日：2022-05-31

申请号：US16849491

申请日：2020-04-15

Applicant: Seagate Technology LLC

Inventor： Naveen Kumar ,  Shuhei Tanakamaru ,  Erich Franz Haratsch

IPC: H03M13/01 ,  H03M13/39 ,  H03M13/11

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

公开(公告)号：US11132244B2

公开(公告)日：2021-09-28

申请号：US16683742

申请日：2019-11-14

Applicant: Seagate Technology LLC

Inventor： Shuhei Tanakamaru ,  Scott McClure ,  Erich Franz Haratsch

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F13/16 ,  G06F12/0882 ,  G06F12/02 ,  G06F11/30

Abstract: A method includes determining a portion of a block of a storage device to read after programming, and reading the portion of the block and determining a maximum error count for the portion of the block. The maximum error count is compared to a threshold. When the maximum error count exceeds the threshold, a code rate of an error correction coding used to program the block is adjusted, or a code rate test is performed on the entire block.

公开(公告)号：US20210149753A1

公开(公告)日：2021-05-20

申请号：US16683742

申请日：2019-11-14

Applicant: Seagate Technology LLC

Inventor： Shuhei Tanakamaru ,  Scott McClure ,  Erich Franz Haratsch

IPC: G06F11/07 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0882 ,  G06F12/02 ,  G06F13/16

Abstract: A method includes determining a portion of a block of a storage device to read after programming, and reading the portion of the block and determining a maximum error count for the portion of the block. The maximum error count is compared to a threshold. When the maximum error count exceeds the threshold, a code rate of an error correction coding used to program the block is adjusted, or a code rate test is performed on the entire block.

公开(公告)号：US20210126657A1

公开(公告)日：2021-04-29

申请号：US16667491

申请日：2019-10-29

Applicant: Seagate Technology LLC

Inventor： Shuhei Tanakamaru ,  Scott McClure ,  Erich Franz Haratsch

IPC: H03M13/35 ,  G06F11/10

Abstract: A method includes programming data in a block of a storage device, and reading back the programmed data and determining a maximum error count for the block. A code rate index that satisfies correction of the maximum error count for the block is determined. A current code rate index is adjusted to the code rate index that satisfies correction of the maximum error count for the block.

公开(公告)号：US11347394B2

公开(公告)日：2022-05-31

申请号：US16983992

申请日：2020-08-03

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Shuhei Tanakamaru ,  Dana Lynn Simonson ,  Erich Franz Haratsch

IPC: G06F3/06 ,  G06F9/48

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

公开(公告)号：US11133831B2

公开(公告)日：2021-09-28

申请号：US16667491

申请日：2019-10-29

Applicant: Seagate Technology LLC

Inventor： Shuhei Tanakamaru ,  Scott McClure ,  Erich Franz Haratsch

IPC: G11C29/00 ,  H03M13/35 ,  G06F11/10

Abstract: A method includes programming data in a block of a storage device, and reading back the programmed data and determining a maximum error count for the block. A code rate index that satisfies correction of the maximum error count for the block is determined. A current code rate index is adjusted to the code rate index that satisfies correction of the maximum error count for the block.