Invention Grant
- Patent Title: Top via stack
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Application No.: US17496252Application Date: 2021-10-07
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Publication No.: US11600565B2Publication Date: 2023-03-07
- Inventor: Brent Alan Anderson , Lawrence A. Clevenger , Christopher J. Penny , Kisik Choi , Nicholas Anthony Lanzillo , Robert Robison
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Daniel Yeates
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/522 ; H01L23/528 ; H01L23/532

Abstract:
A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.
Public/Granted literature
- US20220028783A1 TOP VIA STACK Public/Granted day:2022-01-27
Information query
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