Invention Grant
- Patent Title: Sub-fin leakage reduction for template strained materials
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Application No.: US16457347Application Date: 2019-06-28
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Publication No.: US11600696B2Publication Date: 2023-03-07
- Inventor: Rishabh Mehandru , Stephen Cea , Anupama Bowonder , Juhyung Nam , Willy Rachmady
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; H01L29/423 ; H01L29/66

Abstract:
Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.
Information query
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