Invention Grant
- Patent Title: Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays
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Application No.: US17161504Application Date: 2021-01-28
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Publication No.: US11610914B2Publication Date: 2023-03-21
- Inventor: Tianhong Yan , Scott Brad Herner , Jie Zhou , Wu-Yi Henry Chien , Eli Harari
- Applicant: Sunrise Memory Corporation
- Applicant Address: US CA San Jose
- Assignee: Sunrise Memory Corporation
- Current Assignee: Sunrise Memory Corporation
- Current Assignee Address: US CA San Jose
- Agency: VLP Law Group LLP
- Agent Edward C. Kwok
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L23/522 ; H01L23/528 ; H01L29/24 ; H01L29/16 ; H01L29/161 ; H01L29/04

Abstract:
A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
Public/Granted literature
- US20210210506A1 VERTICAL THIN-FILM TRANSISTOR AND APPLICATION AS BIT-LINE CONNECTOR FOR 3-DIMENSIONAL MEMORY ARRAYS Public/Granted day:2021-07-08
Information query
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