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    Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same
    2.
    发明授权
    Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same 有权

    公开(公告)号：US11937424B2

    公开(公告)日：2024-03-19

    申请号：US17458029

    申请日：2021-08-26

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Scott Brad Herner ,  Eli Harari

    IPC分类号： H10B43/20

    CPC分类号： H10B43/20

    摘要： A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers. In this configuration, the first, second and third semiconductor layers and the first conductor provide a channel region, a drain region, a source region and a gate electrode of the thin-film storage transistor.

    MEMORY CONTROLLER FOR A HIGH CAPACITY MEMORY CIRCUIT WITH LARGE NUMBER OF INDEPENDENTLY ACCESSIBLE MEMORY BANKS
    5.
    发明公开
    MEMORY CONTROLLER FOR A HIGH CAPACITY MEMORY CIRCUIT WITH LARGE NUMBER OF INDEPENDENTLY ACCESSIBLE MEMORY BANKS 审中-公开

    公开(公告)号：US20240045615A1

    公开(公告)日：2024-02-08

    申请号：US18357948

    申请日：2023-07-24

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Shay Fux ,  Sagie Goldenberg ,  Amotz Yagev

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0656 ,  G06F3/0659 ,  G06F3/0611 ,  G06F3/0679

    摘要： A memory system includes a memory device including an array of storage transistors for storing data where the storage transistors are organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device.

    MEMORY STRUCTURE INCLUDING THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC MEMORY TRANSISTORS AND METHOD OF FABRICATION
    9.
    发明公开
    MEMORY STRUCTURE INCLUDING THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC MEMORY TRANSISTORS AND METHOD OF FABRICATION 审中-公开

    公开(公告)号：US20230262988A1

    公开(公告)日：2023-08-17

    申请号：US17936320

    申请日：2022-09-28

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Eli Harari

    IPC分类号： H01L27/11597 ,  H01L27/1159 ,  H01L27/11592

    CPC分类号： H01L27/11597 ,  H01L27/1159 ,  H01L27/11592

    摘要： A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The three-dimensional memory stacks are manufactured in a process that includes forming operational trenches for vertical local word lines and forming auxiliary trenches to facilitate back-alley metal replacement and channel separation by a backside selective etch process. In some embodiments, the ferroelectric storage transistors are junctionless field-effect transistors (FeFETs) having a ferroelectric polarization layer as the gate dielectric layer formed adjacent a semiconductor oxide layer as the channel region.

    MEMORY STRUCTURE OF THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC MEMORY TRANSISTORS INCORPORATING AIR GAP ISOLATION STRUCTURES
    10.
    发明公开
    MEMORY STRUCTURE OF THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC MEMORY TRANSISTORS INCORPORATING AIR GAP ISOLATION STRUCTURES 审中-公开

    公开(公告)号：US20230262987A1

    公开(公告)日：2023-08-17

    申请号：US17936315

    申请日：2022-09-28

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Eli Harari ,  Kavita Shah

    IPC分类号： H01L27/11597 ,  G11C16/04 ,  H01L27/11587

    CPC分类号： H01L27/11597 ,  G11C16/0483 ,  H01L27/11587

    摘要： A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The three-dimensional memory stacks are manufactured in a process that includes forming operational trenches for vertical local word lines and forming auxiliary trenches to facilitate back-alley metal replacement and channel separation by a backside selective etch process. In some embodiments, the ferroelectric storage transistors are junctionless field-effect transistors (FeFETs) having a ferroelectric polarization layer as the gate dielectric layer formed adjacent a semiconductor oxide layer as the channel region. In some embodiments, ferroelectric storage transistors in the memory stacks are isolated by air gap cavities.