Invention Grant
- Patent Title: Implementing mapping data structures to minimize sequentially written data accesses
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Application No.: US17487396Application Date: 2021-09-28
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Publication No.: US11615020B2Publication Date: 2023-03-28
- Inventor: Naveen Bolisetty
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Priority: IN202141036475 20210812
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/02 ; G06F12/1045 ; G06F3/06 ; G06F12/1009 ; G06F12/1027

Abstract:
A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including receiving a request to sequentially write data to a block of a memory device, in response to receiving the request, writing the data to the block to obtain sequentially written data, initiating accumulation of logical-to-physical (L2P) mapping data corresponding to the sequentially written data, determining that a criterion for terminating the accumulation of the L2P mapping data is satisfied, in response to determining that the criterion is satisfied, terminating the accumulation of the L2P mapping data to obtain accumulated L2P mapping data, and updating an L2P mapping data structure based on the accumulated L2P mapping data.
Public/Granted literature
- US20230048104A1 IMPLEMENTING MAPPING DATA STRUCTURES TO MINIMIZE SEQUENTIALLY WRITTEN DATA ACCESSES Public/Granted day:2023-02-16
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