公开(公告)号：US20240069806A1

公开(公告)日：2024-02-29

申请号：US17899092

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: A system and method for managing data compaction in zones in memory devices. An example method includes receiving, by a processor of a memory device, receiving, by a processing device, a write command; identifying a zoned namespace (ZNS) zone specified with the write command; selecting a first subset of memory pages of a first management unit that is configured to store a first number of bits per memory cell, wherein the first management unit is associated with the ZNS zone; accessing a capacity counter associated with the ZNS zone that reflects an amount of data currently stored to the ZNS zone; and responsive to determining that the capacity counter satisfies a threshold criterion, causing the memory device to copy the data associated with the ZNS zone from the first subset of memory pages to a second subset of memory pages of a second management unit of the memory device.

公开(公告)号：US11487609B2

公开(公告)日：2022-11-01

申请号：US17375301

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty ,  Rajeshwar Kailash

IPC: G11C29/00 ,  G06F11/10

Abstract: A system includes a memory device including a first unit, and a processing device, operatively coupled to the memory device, to perform operations including identifying a set of parity data on a volatile memory, determining whether the set of parity data satisfies a condition pertaining to a size of the set of parity data, and responsive to determining that the set of parity data does not satisfy the condition, appending parity data to the set of parity data. The parity data is generated based on a set of host data written on the first unit.

公开(公告)号：US11836076B2

公开(公告)日：2023-12-05

申请号：US18105327

申请日：2023-02-03

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/1045 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/0246 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1054 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/7201

Abstract: A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including storing, on a volatile memory device, logical-to-physical (L2P) mapping data corresponding to sequentially written data, determining whether an L2P update criterion is satisfied, and in response to determining that the L2P update criterion is satisfied, updating an L2P mapping data structure based on the L2P mapping data. The L2P mapping data structure maintains an initial logical translation unit (LTU) of the sequentially written data, and a length of the sequentially written data from the initial LTU.

公开(公告)号：US11615020B2

公开(公告)日：2023-03-28

申请号：US17487396

申请日：2021-09-28

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/1045 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/1027

Abstract: A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including receiving a request to sequentially write data to a block of a memory device, in response to receiving the request, writing the data to the block to obtain sequentially written data, initiating accumulation of logical-to-physical (L2P) mapping data corresponding to the sequentially written data, determining that a criterion for terminating the accumulation of the L2P mapping data is satisfied, in response to determining that the criterion is satisfied, terminating the accumulation of the L2P mapping data to obtain accumulated L2P mapping data, and updating an L2P mapping data structure based on the accumulated L2P mapping data.

公开(公告)号：US20210342219A1

公开(公告)日：2021-11-04

申请号：US17375301

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty ,  Rajeshwar Kailash

IPC: G06F11/10

Abstract: A system includes a memory device including a first unit, and a processing device, operatively coupled to the memory device, to perform operations including identifying a set of parity data on a volatile memory, determining whether the set of parity data satisfies a condition pertaining to a size of the set of parity data, and responsive to determining that the set of parity data does not satisfy the condition, appending parity data to the set of parity data. The parity data is generated based on a set of host data written on the first unit.

公开(公告)号：US20210191808A1

公开(公告)日：2021-06-24

申请号：US16834534

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj ,  Naveen Bolisetty ,  Suman Kumari

IPC: G06F11/10 ,  G06F12/0882 ,  G06F12/02 ,  G06F9/30

Abstract: Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

公开(公告)号：US20250036319A1

公开(公告)日：2025-01-30

申请号：US18918461

申请日：2024-10-17

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty

IPC: G06F3/06

Abstract: A system and method for managing data compaction in zones in memory devices. An example method includes responsive to determining that a capacity counter associated with a first zoned namespace (ZNS) zone satisfies a threshold criterion, causing a memory device to copy, from a first management unit of the memory device to a second management unit of the memory device, first data associated with the first ZNS zone, wherein the first management unit comprises a first subset of memory pages configured to store a first number of bits per memory cell and the second management unit comprises a second subset of memory pages configured to store a second number of bits per memory cell; and causing the memory device to copy, from the first management unit to a third management unit of the memory device, second data associated with a second ZNS zone.

公开(公告)号：US11953973B2

公开(公告)日：2024-04-09

申请号：US17809731

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty ,  Tingjun Xie

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/076 ,  G06F11/073

Abstract: In some implementations, a memory device may detect a first read failure associated with a page type and a memory section of the memory device. The memory device may perform multiple read recovery operations in a first order defined by a first sequence of read recovery operations. The memory device may identify a read recovery operation that results in successful recovery from the first read failure. The memory device may reorder the first sequence of read recovery operations to generate a second sequence of read recovery operations that prioritizes the read recovery operation. The memory device may detect a second read failure associated with the page type and the memory section. The memory device may perform one or more read recovery operations to recover from the second read failure in a second order defined by the second sequence of read recovery operations.

公开(公告)号：US11630725B2

公开(公告)日：2023-04-18

申请号：US16834534

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj ,  Naveen Bolisetty ,  Suman Kumari

IPC: G06F11/00 ,  G06F11/10 ,  G06F9/30 ,  G06F12/02 ,  G06F12/0882

Abstract: Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

公开(公告)号：US20230025508A1

公开(公告)日：2023-01-26

申请号：US17492143

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty ,  Peng Fei ,  Yiran Liu ,  Shakeel Bukhari

IPC: G06F3/06

Abstract: A method is described, which includes receiving, by a memory subsystem controller from a host system, a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device. The controller converts the set of logical block addresses to a set of physical block addresses for the set of transfer units; generates a set of device read memory commands based on the physical block addresses, wherein each device read memory command references at least one physical block address; and generates a first aggregated device read memory command based on a first device read memory command and a second read memory command in response to determining that the first device read memory command is associated with the second device read memory command. The controller thereafter transmits the first aggregated device read memory command to the memory device.