Non volatile flash memory with improved verification recovery and column seeding
Abstract:
An apparatus is described. The apparatus includes a non volatile memory chip. The non volatile memory chip includes an interface to receive access commands, a three dimensional array of non volatile storage cells, and, a controller to orchestrate removal of charge in a column of stacked ones of the non volatile storage cells after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount. The removal of the charge pushes the charge out of the column by changing respective word line potentials along a particular direction along the column. Cells that are coupled to the column are programmed in the particular direction. Disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction.
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