- Patent Title: Semiconductor device including gate layer and vertical structure
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Application No.: US17749486Application Date: 2022-05-20
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Publication No.: US11626413B2Publication Date: 2023-04-11
- Inventor: Junhyoung Kim , Jisung Cheon
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Lee IP Law, P.C.
- Priority: KR10-2019-0081435 20190705
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11575 ; H01L27/11524 ; H01L27/11548 ; H01L27/1157

Abstract:
A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.
Public/Granted literature
- US20220278118A1 SEMICONDUCTOR DEVICE INCLUDING GATE LAYER AND VERTICAL STRUCTURE Public/Granted day:2022-09-01
Information query
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