公开(公告)号：US12219763B2

公开(公告)日：2025-02-04

申请号：US17744092

申请日：2022-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon ,  Byunggon Park ,  Joowon Park ,  Sangjun Hong ,  Jinsoo Lim

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.

公开(公告)号：US11626413B2

公开(公告)日：2023-04-11

申请号：US17749486

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157

Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

公开(公告)号：US12096634B2

公开(公告)日：2024-09-17

申请号：US18132019

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

公开(公告)号：US11672119B2

公开(公告)日：2023-06-06

申请号：US17028029

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon ,  Jiye Noh ,  Byunggon Park ,  Jinsoo Lim

IPC: H01L29/788 ,  H01L27/11582 ,  G11C7/18 ,  H01L23/522 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/11565

Abstract: A vertical memory device includes a gate electrode structure, channels, a charge storage structure, and a division pattern. The gate electrode includes gate electrodes spaced apart from each other in a first direction. The channel extends through the gate electrode structure, and includes a first portion and a second portion on and contacting the first portion. The second portion includes a lower surface having a width less than that of an upper surface of the first portion. The charge storage structure covers an outer sidewall of the channel. The division pattern extends between the channels in a second direction, and includes a first dummy channel and a first dummy charge storage structure covering a sidewall and a lower surface thereof. The first dummy channel includes the same material as that the channel, and the first dummy charge storage structure includes the same material as the charge storage structure.

公开(公告)号：US11557604B2

公开(公告)日：2023-01-17

申请号：US17025120

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyeon Woo ,  Sangjun Hong ,  Jinsoo Lim ,  Jisung Cheon

IPC: H01L27/11582 ,  H01L27/11565 ,  G11C8/14 ,  H01L27/11556 ,  H01L27/11519

Abstract: A semiconductor device includes: a first gate stack including a plurality of first gate electrodes; a second gate stack arranged on the first gate stack and including a plurality of second gate electrodes; and a plurality of channel structures arranged in a plurality of channel holes penetrating the first gate stack and the second gate stack. Each of the channel holes includes a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, and a ratio of a second width in the second direction to a first width in the first direction of an upper end of the first channel hole portion is less than a ratio of a fourth width in the second direction to a third width in the first direction of an upper end of the second channel hole portion.

公开(公告)号：US20210151452A1

公开(公告)日：2021-05-20

申请号：US16903990

申请日：2020-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisung Cheon ,  Kiyoon Kang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/792 ,  G11C5/02 ,  G11C5/06

Abstract: A memory device may include a substrate; a first stack structure comprising a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; a second stack structure comprising a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stack structure; and a channel structure penetrating the first stack structure and the second stack structure, wherein the channel structure comprises a first portion in a first channel hole penetrating the first stack structure, a second portion in a second channel hole penetrating the second stack structure, and a first protrusion located in a first recess recessed into one layer of the plurality of first interlayer insulating layers from a side portion of the first channel hole.

公开(公告)号：US20220328522A1

公开(公告)日：2022-10-13

申请号：US17854356

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joowon Park ,  Woongseop Lee ,  Eiwhan Jung ,  Jisung Cheon

IPC: H01L27/11582 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/522

Abstract: A semiconductor device includes a peripheral circuit region on a first substrate and including circuit devices, a memory cell region on a second substrate overlaid on the first substrate, with the memory cell region including gate electrodes stacked to be spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and channel structures which extend vertically on the second substrate and penetrate through the gate electrodes. The channel structures may include a channel layer. The semiconductor device includes a through-wiring region with through-contact plugs that extend in the first direction and that electrically connect the memory cell region and the peripheral circuit region to each other, with the through-wiring region including an insulating region that surrounds the through-contact plugs. The through-wiring region further includes dummy channel structures regularly arranged throughout the through-wiring region and which include the channel layer.

公开(公告)号：US11437396B2

公开(公告)日：2022-09-06

申请号：US17032128

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US11335695B2

公开(公告)日：2022-05-17

申请号：US16710402

申请日：2019-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon ,  Byunggon Park ,  Joowon Park ,  Sangjun Hong ,  Jinsoo Lim

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L23/535

Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.

公开(公告)号：US11069698B2

公开(公告)日：2021-07-20

申请号：US16398442

申请日：2019-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kwang-Soo Kim ,  Geunwon Lim ,  Jisung Cheon

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/311

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.