Invention Grant
- Patent Title: Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions
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Application No.: US17498468Application Date: 2021-10-11
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Publication No.: US11626481B2Publication Date: 2023-04-11
- Inventor: Zailong Bian , Janos Fucsko
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/764 ; H01L27/11521 ; H01L27/105 ; H01L21/762 ; H01L27/115 ; H01L29/78
Abstract:
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
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