Invention Grant
- Patent Title: Method of fabricating self-aligned via structures
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Application No.: US17671394Application Date: 2022-02-14
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Publication No.: US11631639B2Publication Date: 2023-04-18
- Inventor: Chieh-Han Wu , Cheng-Hsiung Tsai , Chih Wei Lu , Chung-Ju Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L23/532 ; H01L21/00

Abstract:
Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
Public/Granted literature
- US20220165661A1 SELF-ALIGNED VIA STRUCTURES AND METHODS Public/Granted day:2022-05-26
Information query
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