In one embodiment, an apparatus includes a clock generator circuit to receive a first clock signal at a first frequency and output a second clock signal at a second frequency less than the first clock frequency. The clock generator circuit may include: a divider circuit to divide the first clock signal to obtain at least a first divided clock signal and a second divided clock signal; and a gating circuit coupled to the divider circuit, the gating circuit to gate the first clock signal with at least one of the first divided clock signal and the second divided clock signal to output the second clock signal.