Invention Grant
- Patent Title: Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes
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Application No.: US17484393Application Date: 2021-09-24
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Publication No.: US11646861B2Publication Date: 2023-05-09
- Inventor: Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Jason Andrew Thompson , Yvonne Hanson Kleppel
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Jeffrey Ingalls
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.
Public/Granted literature
- US20230098514A1 LOW-LATENCY, HIGH-AVAILABILITY AND HIGH-SPEED SERDES INTERFACE HAVING MULTIPLE SYNCHRONIZATION MODES Public/Granted day:2023-03-30
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