- Patent Title: Methods used in forming integrated circuitry comprising a stack comprising vertically-alternating first tiers and second tiers with the stack comprising a cavity therein that comprises a stair-step structure
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Application No.: US16927293Application Date: 2020-07-13
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Publication No.: US11647633B2Publication Date: 2023-05-09
- Inventor: Jivaan Kishore Jhothiraman , John Mark Meldrim
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/1157
- IPC: H01L27/1157 ; H01L27/11565 ; H01L27/11582
Abstract:
A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.
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