Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.