Invention Grant
- Patent Title: Isolation structures for transistors
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Application No.: US17678213Application Date: 2022-02-23
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Publication No.: US11652002B2Publication Date: 2023-05-16
- Inventor: Shahaji B. More , Chun Hsiung Tsai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L29/66 ; H01L21/02 ; H01L29/78 ; H01L21/762

Abstract:
The present disclosure is directed to methods for the fabrication of gate-all-around (GAA) field effect transistors (FETs) with low power consumption. The method includes depositing a first and a second epitaxial layer on a substrate and etching trench openings in the first and second epitaxial layers and the substrate. The method further includes removing, through the trench openings, portions of the first epitaxial layer to form a gap between the second epitaxial layer and the substrate and depositing, through the trench openings, a first dielectric to fill the gap and form an isolation structure. In addition, the method includes depositing a second dielectric in the trench openings to form trench isolation structures and forming a transistor structure on the second epitaxial layer.
Public/Granted literature
- US20220181502A1 Isolation Structures for Transistors Public/Granted day:2022-06-09
Information query
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