Automated speed ramp control of stepper motor acceleration and deceleration using direct memory access (DMA) and core independent peripherals (CIPs) comprises a numerically controlled oscillator (NCO) controlled through direct memory access (DMA) transfers of prescale values used in combination with a clock oscillator to generate clock pulses that are a function of the clock oscillator frequency and the prescale values. This automates changing the frequency of the NCO, thereby controlling steeper motor speed, without requiring computer processing unit (CPU) overhead. The DMA module is enabled during a first number of clock pulses for step speed acceleration, disabled during a second number of clock pulses for normal operation at full step speed, and then re-enabled during a third number of clock pulses for step speed deceleration. A table in memory may store and provide a plurality of acceleration and deceleration prescale values for DMA transfers to the NCO.