Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.