Invention Grant
- Patent Title: Latch-up avoidance for sea-of-gates
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Application No.: US17411113Application Date: 2021-08-25
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Publication No.: US11663391B2Publication Date: 2023-05-30
- Inventor: David Wolpert , Ryan Michael Kruse , Leon Sigal , Richard Edward Serton , Matthew Stephen Angyal , Terence Hook , Richard Andre Wachnik
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Kelsey M. Skodje
- Main IPC: G06F30/394
- IPC: G06F30/394 ; H01L27/02

Abstract:
Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.
Public/Granted literature
- US20230062945A1 LATCH-UP AVOIDANCE FOR SEA-OF-GATES Public/Granted day:2023-03-02
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