A semiconductor memory device includes a substrate, a first conductor layer, and a first insulator layer. The substrate includes a first region on which memory cells are provided, a second region on which a control circuit of the memory cells is provided, and a third region separating the first region and the second region. The first conductor layer is above the second region of the substrate. The first insulator layer is above the second and third regions of the substrate. The first insulator layer includes a first portion that is above the first conductor layer and extends along a surface direction of the substrate, and a second portion that is continuous with the first portion and extends along a thickness direction of the substrate from the first portion toward a surface of the substrate in the third region.