- Patent Title: Panel level metal wall grids array for integrated circuit packaging
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Application No.: US17469822Application Date: 2021-09-08
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Publication No.: US11670600B2Publication Date: 2023-06-06
- Inventor: Yingjiang Pu , Hunt Hang Jiang , Xiuhong Guo
- Applicant: Chengdu Monolithic Power Systems Co., Ltd.
- Applicant Address: CN Chengdu
- Assignee: Chengdu Monolithic Power Systems Co., Ltd.
- Current Assignee: Chengdu Monolithic Power Systems Co., Ltd.
- Current Assignee Address: CN Chengdu
- Agency: Perkins Coie LLP
- Priority: CN 2010946732.5 2020.09.10
- Main IPC: H01L23/373
- IPC: H01L23/373 ; H01L23/552 ; C25D5/02 ; H01L21/48

Abstract:
A panel-shaped metal wall grids array for panel level IC packaging and associated manufacturing method. Each metal wall grid in the metal wall grids array has a continuous and closed metal wall of a predetermined wall height. The metal wall grids are connected to form a monolithic panel through a plurality of metal connecting portions. When the panel-shaped metal wall grids array is used for panel level IC packaging, at least one IC chip/IC die is disposed in each metal wall grid with a top surface of each IC chip/IC die facing downwards, and a panel-shaped metal layer matching with the panel-shaped wall grids array may be further formed on the entire back side of the panel-shaped metal wall grids array so that the panel-shaped metal layer is bonded to the metal wall of each metal wall grid.
Public/Granted literature
- US20220077075A1 PANEL LEVEL METAL WALL GRIDS ARRAY FOR INTEGRATED CIRCUIT PACKAGING AND ASSOCIATED MANUFACTURING METHOD Public/Granted day:2022-03-10
Information query
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