Invention Grant
- Patent Title: Memory array structures for capacitive sense NAND memory
-
Application No.: US17557389Application Date: 2021-12-21
-
Publication No.: US11678482B2Publication Date: 2023-06-13
- Inventor: Yoshiaki Fukuzumi , Jun Fujiki , Shuji Tanaka , Masashi Yoshida , Masanobu Saito , Yoshihiko Kamata
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; G11C5/02 ; G11C5/06 ; G11C16/34 ; H01L27/11582
Abstract:
Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.
Public/Granted literature
- US20220181346A1 MEMORY ARRAY STRUCTURES FOR CAPACITIVE SENSE NAND MEMORY Public/Granted day:2022-06-09
Information query
IPC分类:
