Invention Grant
- Patent Title: Reducing power for memory subsystem and having latency for power delivery network
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Application No.: US17371815Application Date: 2021-07-09
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Publication No.: US11681446B2Publication Date: 2023-06-20
- Inventor: Mohamed Roumi , Sushil Kumar , Tushar Chhabra , Sharath Chandra Ambula
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06

Abstract:
Methods, systems, and devices for power supply control for non-volatile memory are described. A package containing a memory subsystem may include a controller, a volatile memory, and a non-volatile memory. The package may include one or more pins for receiving a supply voltage that may be distributed to the controller, the volatile memory, and the non-volatile memory using one or more power supply rails. The memory subsystem may include one or more switching components along one or more power supply rails to selectively decouple the non-volatile memory from the one or more power supply rails, thereby enabling the non-volatile memory to be powered down separately from the controller and volatile memory. The controller may determine whether to couple or uncouple the non-volatile memory from a power supply rail based on various criteria associated with accessing the non-volatile memory.
Public/Granted literature
- US20220011951A1 REDUCING POWER FOR MEMORY SUBSYSTEM AND HAVING LATENCY FOR POWER DELIVERY NETWORK Public/Granted day:2022-01-13
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