公开(公告)号：US20220011951A1

公开(公告)日：2022-01-13

申请号：US17371815

申请日：2021-07-09

Applicant: Micron Technology, Inc.

Inventor： Mohamed Roumi ,  Sushil Kumar ,  Tushar Chhabra ,  Sharath Chandra Ambula

IPC: G06F3/06

Abstract: Methods, systems, and devices for power supply control for non-volatile memory are described. A package containing a memory subsystem may include a controller, a volatile memory, and a non-volatile memory. The package may include one or more pins for receiving a supply voltage that may be distributed to the controller, the volatile memory, and the non-volatile memory using one or more power supply rails. The memory subsystem may include one or more switching components along one or more power supply rails to selectively decouple the non-volatile memory from the one or more power supply rails, thereby enabling the non-volatile memory to be powered down separately from the controller and volatile memory. The controller may determine whether to couple or uncouple the non-volatile memory from a power supply rail based on various criteria associated with accessing the non-volatile memory.

公开(公告)号：US11681446B2

公开(公告)日：2023-06-20

申请号：US17371815

申请日：2021-07-09

Applicant: Micron Technology, Inc.

Inventor： Mohamed Roumi ,  Sushil Kumar ,  Tushar Chhabra ,  Sharath Chandra Ambula

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems, and devices for power supply control for non-volatile memory are described. A package containing a memory subsystem may include a controller, a volatile memory, and a non-volatile memory. The package may include one or more pins for receiving a supply voltage that may be distributed to the controller, the volatile memory, and the non-volatile memory using one or more power supply rails. The memory subsystem may include one or more switching components along one or more power supply rails to selectively decouple the non-volatile memory from the one or more power supply rails, thereby enabling the non-volatile memory to be powered down separately from the controller and volatile memory. The controller may determine whether to couple or uncouple the non-volatile memory from a power supply rail based on various criteria associated with accessing the non-volatile memory.