Invention Grant
- Patent Title: High aspect ratio vias for integrated circuits
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Application No.: US17129971Application Date: 2020-12-22
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Publication No.: US11682617B2Publication Date: 2023-06-20
- Inventor: Nicholas Anthony Lanzillo , Somnath Ghosh , Lawrence A. Clevenger , Robert Robison
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Grant M. McNeilly
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L21/768

Abstract:
An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.
Public/Granted literature
- US20220199521A1 HIGH ASPECT RATIO VIAS FOR INTEGRATED CIRCUITS Public/Granted day:2022-06-23
Information query
IPC分类: