公开(公告)号：US20220199521A1

公开(公告)日：2022-06-23

申请号：US17129971

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Somnath Ghosh ,  Lawrence A. Clevenger ,  Robert Robison

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.

公开(公告)号：US20210265201A1

公开(公告)日：2021-08-26

申请号：US16796079

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Daniel James Dechene ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033

Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

公开(公告)号：US20210210379A1

公开(公告)日：2021-07-08

申请号：US16736478

申请日：2020-01-07

Applicant: International Business Machines Corporation

Inventor： Daniel James Dechene ,  Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

公开(公告)号：US12020949B2

公开(公告)日：2024-06-25

申请号：US17447388

申请日：2021-09-10

Applicant: International Business Machines Corporation

Inventor： Dominik Metzler ,  Somnath Ghosh ,  John Christopher Arnold ,  Ekmini Anuja De Silva

IPC: H01L21/3213 ,  H01L21/768 ,  G06F30/3953

CPC classification number: H01L21/32139 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76885 ,  G06F30/3953

Abstract: A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.

公开(公告)号：US11990412B2

公开(公告)日：2024-05-21

申请号：US17488389

申请日：2021-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Stuart Sieg ,  Somnath Ghosh ,  Kisik Choi ,  Rishikesh Krishnan ,  Alexander Reznicek

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L23/5286 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392

Abstract: Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

公开(公告)号：US20230207553A1

公开(公告)日：2023-06-29

申请号：US17562331

申请日：2021-12-27

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Somnath Ghosh ,  Sagarika Mukesh ,  Albert Chu ,  Albert M. Young ,  Balasubramanian S. Pranatharthiharan ,  Huiming Bu ,  Kai Zhao ,  John Christopher Arnold ,  Brent A. Anderson ,  Dechao Guo

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L27/0207 ,  H01L29/42392 ,  H01L29/0673 ,  H01L27/092 ,  H01L27/1251 ,  H01L21/823475 ,  H01L21/76229

Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

公开(公告)号：US11688636B2

公开(公告)日：2023-06-27

申请号：US17351307

申请日：2021-06-18

Applicant: International Business Machines Corporation

Inventor： Somnath Ghosh ,  Karen Elizabeth Petrillo ,  Cody J. Murray ,  Ekmini Anuja De Silva ,  Chi-Chun Liu ,  Dominik Metzler ,  John Christopher Arnold

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L21/76892 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76837 ,  H01L23/53242

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

公开(公告)号：US11217481B2

公开(公告)日：2022-01-04

申请号：US16678053

申请日：2019-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Koichi Motoyama ,  Somnath Ghosh ,  Christopher J. Penny ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

公开(公告)号：US11062943B2

公开(公告)日：2021-07-13

申请号：US16536785

申请日：2019-08-09

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Somnath Ghosh ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/311

Abstract: A method includes patterning an interconnect trench in a dielectric layer. The interconnect trench has sidewalk and a bottom surface. A liner layer is deposited on the sidewalls and the bottom surface of the interconnect trench. The interconnect trench is filled with a first conductive metal material. The conducting metal material is recessed to below a top surface of the dielectric layer. A cap layer is deposited on a top surface of the first conductive metal material. The cap layer and the liner layer are of the same material. The method further includes forming a via on a portion of the interconnect trench.

公开(公告)号：US11024551B1

公开(公告)日：2021-06-01

申请号：US16735857

申请日：2020-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Daniel James Dechene ,  Somnath Ghosh ,  Carl Radens

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A method is presented for forming a multi-level of interconnects underneath a complementary metal oxide semiconductor (CMOS) device. The method includes forming a stack including alternating layers of a semiconductor material and a first conductive material, patterning vias in the stack to define multiple stacks, depositing a first block material within each of the vias, forming a series of first block materials within a first via, forming a series of second block materials within a second via, the first and second vias being on opposed ends of a stack of the multiple stacks, and performing vertical metallization between the first block material and the series of first block materials in the first via, and between the first block material and the series of second block materials in the second via.