- 专利标题: Priority-based cache-line fitting in compressed memory systems of processor-based systems
-
申请号: US17572472申请日: 2022-01-10
-
公开(公告)号: US11687461B1公开(公告)日: 2023-06-27
- 发明人: Norris Geng , Richard Senior , Gurvinder Singh Chhabra , Kan Wang
- 申请人: QUALCOMM Incorporated
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM Incorporated
- 当前专利权人: QUALCOMM Incorporated
- 当前专利权人地址: US CA San Diego
- 代理机构: W&T
- 主分类号: G06F12/084
- IPC分类号: G06F12/084 ; G06F12/0811 ; G06F3/06
摘要:
A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.
公开/授权文献
信息查询
IPC分类: