公开(公告)号：US11829292B1

公开(公告)日：2023-11-28

申请号：US17572472

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/084 ,  G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0811

Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.

公开(公告)号：US11687461B1

公开(公告)日：2023-06-27

申请号：US17572472

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/084 ,  G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0811

Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.

公开(公告)号：US11868244B2

公开(公告)日：2024-01-09

申请号：US17572471

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/401

Abstract: A compressed memory system of a processor-based system includes a memory partitioning circuit for partitioning a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high priority data region and a second cache line from a low priority data region. The system also includes a compression circuit for compressing the cache lines to obtain a first and a second compressed cache line. The system also includes a cache line packing circuit for packing the compressed cache lines such that the first compressed cache line is written to a first predetermined portion and the second cache line or a portion of the second compressed cache line is written to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.