Invention Grant
- Patent Title: Host-resident translation layer validity check techniques
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Application No.: US17576466Application Date: 2022-01-14
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Publication No.: US11687469B2Publication Date: 2023-06-27
- Inventor: David Aaron Palmer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F21/00
- IPC: G06F21/00 ; G06F12/14 ; G06F12/06 ; G06F21/60
Abstract:
Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
Public/Granted literature
- US20220206959A1 HOST-RESIDENT TRANSLATION LAYER VALIDITY CHECK TECHNIQUES Public/Granted day:2022-06-30
Information query
