公开(公告)号：US12050804B2

公开(公告)日：2024-07-30

申请号：US17942821

申请日：2022-09-12

申请人： Micron Technology, Inc.

发明人： David Aaron Palmer

IPC分类号： G06F3/06 ,  G06F12/10

CPC分类号： G06F3/0653 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/10 ,  G06F2212/657

摘要： Methods, systems, and devices for valid data aware media reliability scanning are described. An apparatus may include a memory array comprising a plurality of blocks and a controller coupled with the memory array. The controller may be configured to select a block of the plurality of blocks for a scan operation to determine a margin of reliability for a first set of data stored in the block. The controller may identify information associated with a status of a validity of sub-blocks of the first set of data in the block. The controller may determine a first subset of the sub-blocks storing valid data of the first set of data and a second subset of sub-blocks that are invalid based on identifying the information. The controller may perform the scan operation on the first subset of sub-blocks and not on the second subset of sub-blocks in the block.

公开(公告)号：US12007889B2

公开(公告)日：2024-06-11

申请号：US17968607

申请日：2022-10-18

申请人： Micron Technology, Inc.

发明人： David Aaron Palmer

IPC分类号： G06F12/02 ,  G06F12/0891

CPC分类号： G06F12/0292 ,  G06F12/0253 ,  G06F12/0891

摘要： Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.

公开(公告)号：US20240176534A1

公开(公告)日：2024-05-30

申请号：US18521693

申请日：2023-11-28

申请人： Micron Technology, Inc.

发明人： David Aaron Palmer

IPC分类号： G06F3/06

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

摘要： Methods, systems, and devices for techniques for improved write performance modes are described. A memory system and a host system may support a high performance mode to write data to the memory system. For example, the host system may provision a dedicated logical unit of the memory system. Upon detecting an urgent situation, the host system may transmit a command to the memory system to enter the high performance mode. In response to the command, the memory system may abort ongoing operations, such as internal memory management operations. Additionally, the host system and the memory system may configure operational parameters to increase the speed of write operations, such as a trim set for writing data to the logical unit, a bit rate of data transfer between the host system and the memory system, clock speeds of the memory system, or a combination thereof.

公开(公告)号：US11966600B2

公开(公告)日：2024-04-23

申请号：US17725119

申请日：2022-04-20

申请人： Micron Technology, Inc.

发明人： Deping He ,  David Aaron Palmer

IPC分类号： G06F3/06

CPC分类号： G06F3/0631 ,  G06F3/0614 ,  G06F3/0641 ,  G06F3/0653 ,  G06F3/0683

摘要： Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

公开(公告)号：US11960398B2

公开(公告)日：2024-04-16

申请号：US16999985

申请日：2020-08-21

申请人： Micron Technology, Inc.

发明人： Deping He ,  David Aaron Palmer

IPC分类号： G06F12/00 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0882 ,  G06F12/0891

CPC分类号： G06F12/0811 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/0882 ,  G06F12/0891

摘要： Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

公开(公告)号：US11892956B2

公开(公告)日：2024-02-06

申请号：US17111195

申请日：2020-12-03

申请人： Micron Technology, Inc.

发明人： Kulachet Tanpairoj ,  Christian M. Gyllenskog ,  David Aaron Palmer

IPC分类号： G06F13/12 ,  G06F13/16 ,  G06F13/24 ,  G06F12/0868 ,  G06F11/30 ,  G06F12/02

CPC分类号： G06F13/1668 ,  G06F11/3037 ,  G06F11/3058 ,  G06F12/0238 ,  G06F12/0868 ,  G06F13/24

摘要： Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

公开(公告)号：US11797380B2

公开(公告)日：2023-10-24

申请号：US17647700

申请日：2022-01-11

申请人： Micron Technology, Inc.

发明人： David Aaron Palmer ,  Jonathan S. Parry

IPC分类号： G06F12/02 ,  G06F11/10 ,  G06F11/07 ,  G06F11/14

CPC分类号： G06F11/1068 ,  G06F11/0772 ,  G06F11/142 ,  G06F11/1417 ,  G06F12/0238

摘要： Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.

公开(公告)号：US11755214B2

公开(公告)日：2023-09-12

申请号：US17702217

申请日：2022-03-23

申请人： Micron Technology, Inc.

发明人： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0631 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7204

摘要： Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US11687277B2

公开(公告)日：2023-06-27

申请号：US16293261

申请日：2019-03-05

申请人： Micron Technology, Inc.

发明人： David Aaron Palmer

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

摘要： Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include initiating a first plurality of host-requested NAND memory operations of a first type at a first channel of a memory device for a first interval, and, at the completion of the first interval, performing a second plurality of homogeneous, host-requested NAND memory operations of a second type at the first multiple plane memory die for a second interval.

公开(公告)号：US11681461B2

公开(公告)日：2023-06-20

申请号：US17532020

申请日：2021-11-22

申请人： Micron Technology, Inc.

发明人： Nadav Grosz ,  David Aaron Palmer

IPC分类号： G06F3/06

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

摘要： Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can he determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.