Invention Grant
- Patent Title: Trenches in wafer level packages for improvements in warpage reliability and thermals
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Application No.: US16526012Application Date: 2019-07-30
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Publication No.: US11688634B2Publication Date: 2023-06-27
- Inventor: Vipul Mehta , Yiqun Bai , Ziyin Lin , John Decker , Yan Li
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/31 ; H01L21/768 ; H01L23/373 ; H01L23/367

Abstract:
Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.
Public/Granted literature
- US20210035859A1 TRENCHES IN WAFER LEVEL PACKAGES FOR IMPROVEMENTS IN WARPAGE RELIABILITY AND THERMALS Public/Granted day:2021-02-04
Information query
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