Invention Grant
- Patent Title: Gate structure and method
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Application No.: US16680816Application Date: 2019-11-12
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Publication No.: US11688791B2Publication Date: 2023-06-27
- Inventor: Ta-Chun Lin , Jhon Jhy Liaw , Kuo-Hua Pan
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/165 ; H01L27/088 ; H01L21/8234 ; H01L21/768 ; H01L21/762 ; H01L21/308 ; H01L21/02 ; H01L21/8238 ; H01L27/092 ; H01L29/786 ; H01L29/423 ; H01L29/10

Abstract:
A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.
Public/Granted literature
- US20200343365A1 Gate Structure and Method Public/Granted day:2020-10-29
Information query
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