公开(公告)号：US20240355896A1

公开(公告)日：2024-10-24

申请号：US18760602

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0274

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US12074057B2

公开(公告)日：2024-08-27

申请号：US18057688

申请日：2022-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/762 ,  G06F30/392 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L21/76283 ,  H01L21/845 ,  H01L29/0649 ,  G06F30/392

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

公开(公告)号：US12057485B2

公开(公告)日：2024-08-06

申请号：US17409086

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L21/027

CPC classification number: H01L29/42392 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0274

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US11742349B2

公开(公告)日：2023-08-29

申请号：US17717296

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.

公开(公告)号：US11688791B2

公开(公告)日：2023-06-27

申请号：US16680816

申请日：2019-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Jhon Jhy Liaw ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

公开(公告)号：US20230081710A1

公开(公告)日：2023-03-16

申请号：US18057688

申请日：2022-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/762 ,  H01L21/84 ,  H01L29/06

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

公开(公告)号：US20210408000A1

公开(公告)日：2021-12-30

申请号：US16917778

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

公开(公告)号：US20200243396A1

公开(公告)日：2020-07-30

申请号：US16853474

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US20190333822A1

公开(公告)日：2019-10-31

申请号：US15964177

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US12051695B2

公开(公告)日：2024-07-30

申请号：US18360166

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.