Invention Grant
- Patent Title: Unified address translation for virtualization of input/output devices
-
Application No.: US16651786Application Date: 2017-12-29
-
Publication No.: US11698866B2Publication Date: 2023-07-11
- Inventor: Utkarsh Y. Kakaiya , Sanjay Kumar , Rajesh M. Sankaran , Philip R. Lantz , Ashok Raj , Kun Tian
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- International Application: PCT/US2017/068938 2017.12.29
- International Announcement: WO2019/132976A 2019.07.04
- Date entered country: 2020-03-27
- Main IPC: G06F12/1009
- IPC: G06F12/1009 ; G06F9/455 ; G06F12/06 ; G06F12/1081

Abstract:
Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.
Public/Granted literature
- US20210173790A1 UNIFIED ADDRESS TRANSLATION FOR VIRTUALIZATION OF INPUT/OUTPUT DEVICES Public/Granted day:2021-06-10
Information query
IPC分类: