Invention Grant
- Patent Title: Method for auto-aligned manufacturing of a VDMOS transistor, and auto-aligned VDMOS transistor
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Application No.: US17322514Application Date: 2021-05-17
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Publication No.: US11705493B2Publication Date: 2023-07-18
- Inventor: Vincenzo Enea
- Applicant: STMICROELECTRONICS S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.r.l.
- Current Assignee: STMICROELECTRONICS S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed Intellectual Property Law Group LLP
- Priority: IT 2017000057056 2017.05.25
- The original application number of the division: US15986181 2018.05.22
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/10 ; H01L29/78 ; H01L29/66 ; H01L21/3065 ; H01L21/308 ; H01L29/40 ; H01L21/266 ; H01L21/265

Abstract:
A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.
Public/Granted literature
- US20210273066A1 METHOD FOR AUTO-ALIGNED MANUFACTURING OF A VDMOS TRANSISTOR, AND AUTO-ALIGNED VDMOS TRANSISTOR Public/Granted day:2021-09-02
Information query
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