Method for auto-aligned manufacturing of a VDMOS transistor, and auto-aligned VDMOS transistor

    公开(公告)号:US11038032B2

    公开(公告)日:2021-06-15

    申请号:US16990606

    申请日:2020-08-11

    Inventor: Vincenzo Enea

    Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

    Method for auto-aligned manufacturing of a VDMOS transistor, and auto-aligned VDMOS transistor

    公开(公告)号:US10770558B2

    公开(公告)日:2020-09-08

    申请号:US16684066

    申请日:2019-11-14

    Inventor: Vincenzo Enea

    Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

    Method for auto-aligned manufacturing of a VDMOS transistor, and auto-aligned VDMOS transistor

    公开(公告)号:US10510849B2

    公开(公告)日:2019-12-17

    申请号:US15986181

    申请日:2018-05-22

    Inventor: Vincenzo Enea

    Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

    Method for auto-aligned manufacturing of a VDMOS transistor, and auto-aligned VDMOS transistor

    公开(公告)号:US12243922B2

    公开(公告)日:2025-03-04

    申请号:US18323317

    申请日:2023-05-24

    Inventor: Vincenzo Enea

    Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

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