Invention Grant
- Patent Title: Adaptive switch biasing scheme for digital-to-analog converter (DAC) performance enhancement
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Application No.: US17337619Application Date: 2021-06-03
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Publication No.: US11705921B2Publication Date: 2023-07-18
- Inventor: Xilin Liu , Nitz Saputra , Behnam Sedighi , Ashok Swaminathan , Dongwon Seo
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson + Sheridan LLP
- Main IPC: H03M1/66
- IPC: H03M1/66 ; H03M1/74 ; H04B1/04 ; G05F3/26 ; H03M1/00 ; H03M1/68

Abstract:
Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.
Public/Granted literature
- US20210391871A1 ADAPTIVE SWITCH BIASING SCHEME FOR DIGITAL-TO-ANALOG CONVERTER (DAC) PERFORMANCE ENHANCEMENT Public/Granted day:2021-12-16
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