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公开(公告)号：US12047085B2
公开(公告)日：2024-07-23
申请号：US18077933
申请日：2022-12-08
发明人： A. Martin Mallinson
IPC分类号： H03M1/00 , G06F5/01 , G06F7/02 , H03F3/04 , H03F3/183 , H03F3/45 , H03G3/00 , H03K5/24 , H03M1/06 , H03M1/34 , H03M1/36
CPC分类号： H03M1/002 , G06F5/01 , G06F7/02 , H03F3/04 , H03F3/183 , H03F3/45089 , H03F3/45475 , H03G3/001 , H03K5/24 , H03M1/34 , H03M1/365 , H03F2203/45528 , H03M1/0682
摘要： An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.
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公开(公告)号：US12040808B2
公开(公告)日：2024-07-16
申请号：US18077917
申请日：2022-12-08
发明人： A. Martin Mallinson
摘要： An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.
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公开(公告)号：US20240178850A1
公开(公告)日：2024-05-30
申请号：US18284803
申请日：2022-03-29
申请人： Viasat Inc.
发明人： Gregory N. Kiesel
IPC分类号： H03M1/00 , H04B17/345
CPC分类号： H03M1/007 , H04B17/345
摘要： A first analog signal may be sampled during a first time period in accordance with a first sampling range and a sampling resolution step size, where a first digital sequence may be outputted during the first time period based on sampling the first analog signal.
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公开(公告)号：US11973479B2
公开(公告)日：2024-04-30
申请号：US17508686
申请日：2021-10-22
发明人： Liuan Zhang , Yulin Tan , Jon Sweat Duster , Ning Zhang , Haigang Feng , Erkan Alpman
CPC分类号： H03G3/3005 , G11B20/10027 , H03G3/001 , H03M1/185 , G11B20/10037
摘要： Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal.
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5.发明授权公开(公告)号：US11967968B2
公开(公告)日：2024-04-23
申请号：US17587972
申请日：2022-01-28
发明人： Paul Thomas Frost , Aditya Vighnesh Ramakanth Bommireddipalli , Hugo Cheung , Abdullah Yilmaz , Ruben Antonio Vasquez
CPC分类号： H03M1/0626
摘要： A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.
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公开(公告)号：US11906877B2
公开(公告)日：2024-02-20
申请号：US17718264
申请日：2022-04-11
申请人： SeeQC Inc.
发明人： Oleg A. Mukhanov , Igor V. Vernik
摘要： A system and method to convert a wideband optical signal to a multi-bit digital electrical signal using a superconducting integrated circuit. In a preferred embodiment, the optical signal modulates the phase (i.e., adjusts the timing) of a sequence of single-flux-quantum voltage pulses. The optoelectronic modulator may comprise an optically tunable Josephson junction, superconducting inductor, or bolometric detector, with switching speeds approaching 100 ps or less. The optical signal may comprise a plurality of optical signals such as a wavelength-division multiplexed signal. The optical-to-digital converter may be applied to high-speed digital communication switches, broadband digital input/output for superconducting or quantum computing, and control/readout of detector arrays.
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公开(公告)号：US11901910B2
公开(公告)日：2024-02-13
申请号：US17862455
申请日：2022-07-12
CPC分类号： H03M1/46
摘要： A successive approximation analog-to-digital with an input for receiving an input analog voltage, and an amplifier with a first set of electrical attributes in a sample phase and a second set of electrical attributes, differing from the first set of electrical attributes, in a conversion phase.
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公开(公告)号：US11888494B2
公开(公告)日：2024-01-30
申请号：US17680544
申请日：2022-02-25
发明人： Masao Iriguchi , Yosuke Goto
CPC分类号： H03M1/1071 , H03M1/002
摘要： A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group.
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公开(公告)号：US20240030923A1
公开(公告)日：2024-01-25
申请号：US18478572
申请日：2023-09-29
IPC分类号： H03K19/0948 , H03K17/16 , H03K19/003 , H03M1/00
CPC分类号： H03K19/0948 , H03K17/161 , H03K19/00346 , H03K19/00369 , H03M1/001
摘要： This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.
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公开(公告)号：US11876528B2
公开(公告)日：2024-01-16
申请号：US17513016
申请日：2021-10-28
申请人： Tsinghua University
发明人： Nan Sun , Yi Zhong , Jiaxin Liu
CPC分类号： H03M1/466 , H03M1/1245
摘要： The present disclosure relates to an analog-to-digital conversion circuit comprising: N sampling and conversion modules connected in parallel, configured to simultaneously sample and sequentially convert first analog signals of N channels to output second analog signals, wherein each of the sampling and conversion modules includes a plurality of sampling capacitors connected in parallel, wherein N is an integer greater than 1; a comparator connected to the N sampling and conversion modules, configured to comparing the second analog signals respectively to obtain comparison signals; and a control module connected to the N sampling and conversion modules and the comparator, configured to control the N sampling and conversion modules to output converted digital signals based on the comparison signals.
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