Invention Grant
- Patent Title: Integrated fuse
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Application No.: US17217005Application Date: 2021-03-30
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Publication No.: US11721647B2Publication Date: 2023-08-08
- Inventor: Pascal Fornara
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Crowe & Dunlevy
- Priority: FR 52417 2018.03.21
- The original application number of the division: US16358223 2019.03.19
- Main IPC: H01L23/62
- IPC: H01L23/62 ; H01H85/02 ; H01L23/525 ; H01L21/66

Abstract:
A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.
Public/Granted literature
- US20210217711A1 INTEGRATED FUSE Public/Granted day:2021-07-15
Information query
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